DS1626S+【PDF 10/12 页】IC THERMOMETER/STAT DIG 8-SOIC

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Sheet目录39

6页 7页 8页 9页 [10页]11页 12页

DS1626/DS1726

10 of 12

Table 4. RESOLUTION CONFIGURATION

RESOLUTION

(BITS)

CONVERSION

TIME (MAX)

(ms)

93.75

187.5

375

750

3-WIRE SERIAL DATA BUS

The 3-wire bus consists of three signals: RST (active-low reset), CLK (clock), and DQ (data). 3-wire

communication is controlled by the RST signal, which functions as chip select signal. All data is

transferred LSb first over the 3-wire bus. All communication with the DS1626/DS1726 is initiated by

driving RST high. Driving RST low terminates communications and causes DQ to go to a high-

impedance state. Note that RST must be toggled low after every communication sequence to ensure that

subsequent commands are recognized by the DS1626/DS1726.

When writing to the DS1626/DS1726, data must be valid during the rising edge of CLK. During read

operations the DS1626/DS1726 output data on DQ on the falling edge of CLK and the data remains valid

through the following rising edge, at which time the DQ pin becomes high impedance until the next

falling edge.

To communicate with the DS1626/DS1726, the master must first drive RST high and then begin

generating the CLK signal while transmitting the desired DS1626/DS1726 command byte. If the

command is a Start Convert T, Stop Convert T, or Software POR command, the transaction is finished

when the last bit of the command has been sent. Figure 7a illustrates a Start Convert T command

sequence.

When writing to the DS1626/DS1726, the master must begin transmitting data during the clock cycle

immediately following the command byte. The DS1626/DS1726 will save only the number of data bits

needed for the specific transaction. For example, for the Write TH or Write TL commands, after twelve

bits of data have been transmitted by the master, the DS1626/DS1726 will ignore any subsequent data

transmitted before RST goes low. Thus, if data is being transmitted in byte-length segments, the

DS1626/DS1726 will load the first twelve bits into the T

ignored. On the other hand, it is necessary to transmit at least the required number of bits for the

requested transaction (i.e., 12-bits to T

or 8-bits to the configuration register), because the

DS1626/DS1726 will not save data until the expected number of bits have been received. Write TH and

Write TL sequences are illustrated in Figure 7b and a Write Config sequence is shown in Figure 7c. Note

that these figures assume byte-wide data transfers.

When reading data from the DS1626/DS1726, the DS1626/DS1726 will begin sending data during the

clock cycle immediately following the command byte. After the last data byte has been sent, the

DS1626/DS1726 will transmit a 0 during each subsequent clock until RST goes low. Figure 7d illustrates

a Read Temperature sequence and a Read Config transaction is shown in Figure 7e. The sequence for

reading the T

or T

registers is the same as the Read Temp transaction in Figure 7d except that the Read

TH or Read TL command is used.

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